BrainScaleS - Neuromorphic processors

Last updated: Aug 14, 2012

The BrainScaleS project aims to understand information processing in the brain at different scales ranging from individual neurons to whole functional brain areas. The research involves three approaches: (1) in vivo biological experimentation; (2) simulation on petascale supercomputers; (3) the construction of neuromorphic processors. The goal is to extract generic theoretical principles of brain function and to use this knowledge to build artificial cognitive systems.

The neuromorphic hardware is based around wafer-scale analog VLSI. Each 20-cm-diameter silicon wafer contains 384 chips, each of which implements 128,000 synapses and up to 512 spiking neurons. This gives a total of around 200,000 neurons and 49 million synapses per wafer. VLSI models operate considerably faster than the biological originals. This allows the emulated neural networks to evolve tens-of-thousands times quicker than real time.

The project is a European consortium of 13 research groups lead by a team at Heidelberg University, Germany. The project started in January 2011 and has funding from the European Union through until the end of 2014.

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Latest news / current status

May 25, 2012  -   New video tour of the neuromorphic hardware shows one artificial spiking neuron triggering the firing of a second neuron.
Jan 23, 2012  -   The fully-assembled wafer-scale system shows its first spikes by the artificial neurons.
Aug 25, 2011  -   Neural network wafers arrive at the lab in Germany, sent from the UMC fabrication plant in Taiwan.

Neuromorphic hardware

The BrainScaleS hardware is based around wafer-scale integration of neuromorphic processors. The silicon wafers are 20 cm in diameter and contain an array of identical, tightly-connected chips. The circuitry is mixed-signal. That is, it contains a mix of both analog and digital circuits. The simulated neurons themselves are analog, while the synaptic weights and interchip communication is digital.

One wafer is built to contain 48 reticles. Each reticle contains 8 HICANN chips (High Input Count Analog Neural Network). This makes a total of 384 identical chips per wafer. A HICANN chip is 5x10 mm2 in size. Each one contains an ANC (Analog Neural Core) which is the central functional block, plus supporting circuitry. Each HICANN implements 128,000 synapses and 512 membrane circuits. These can be grouped together to form simulated neurons.

The number of neurons per chip depends on how many synapses are configured per neuron. For the maximum of 16,000 pre-synaptic inputs per neuron, 8 neurons are possible per chip. For the maximum of 512 neurons per chip, there can only be 256 synapses per neuron.

Thus, per wafer there is a total of 49,152,000 synapses, or up to 196,608 neurons. This is assuming that every chip on the wafer is flawless and functional, which will not necessarily always be the case.

The wafer is supported on an aluminum plate which also serves as a heat sink. A multi-layer printed circuit board (PCB) is placed on top of the wafer and this serves as the input/output interface to the neural circuitry. Larger systems can be built by interconnecting several wafer modules.

The circuitry implements time-continuous leaky integrate-and-fire neurons with conductance-based synapses. Neural networks can be created with both short-term and long-term plasticity mechanism. Because of the timescales involved in the chip operation, the neural networks can be evolved thousands of times faster than their real time biological counterparts. Altogether, the BrainScaleS architecture shows promise for studying Hebbian learning, STDP, and cortical dynamics.

The neuromorphic hardware was designed at the universities in Heidelberg and Dresden. The fabrication was done by UMC in Taiwan.

Supercomputer simulations

Supercomputers are used to perform simulations of large-scale neural networks. The aim is to develop mathematical models of such networks. These models will then be used later to design the neuromorphic hardware.

The simulation work is lead by Professor Markus Diesmann of the Computational Neurophysics group at the Jülich Research Center in the town of Jülich, Germany.

The simulations are run on the JUGENE supercomputer - a Blue Gene/P system installed at Jülich. As of May 2011 this is ranked the 13th fastest supercomputer in the world. It has 294,912 processor cores and a performance of around 1 petaflops.

The simulations are used to test mathematical models of neural circuits. The software used is NEST (NEural Simulation Tool). This simulates networks of point neurons or neurons with a small number of compartments.

Although very large scale networks have been previously investigated, e.g. Izhikevich, the underlying simulation technologies have not been described in sufficient detail to be reproducible by other research groups.

Recent work optimising the memory consumption of NEST showed that a network of 59 million neurons, with 10,000 synapses per neuron, can be distributed over all 294,912 cores of JUGENE. Networks of 100 million neurons and a trillion synapses are also theoretically realizable - either by increasing the number of cores, or reducing the overhead for neurons. This is still about three orders of magnitude away from the human brain, however, which has around 86 billion neurons and 1,000 trillion synapses.

Paper published January 2012: Meeting the memory challenges of brain-scale network simulation

The JUGENE supercomputer is scheduled for decommission for 31 July 2012 and will be replaced by a Blue Gene/Q system called JUQUEEN. It will have 131,072 compute cores and a peak performance of 1.6 petaflops. Each core is an IBM PowerPC A2 running at 1.6 GHz.


BrainScaleS is funded by the European Union. It received €8.5 million initially, plus €700,000 in an extension.

The funding comes from the Brain ICT program, which in turn is part of the Seventh Framework Programme (FP7).

The project is set to run from January 1, 2011 until December 31, 2014.


31.Aug.2010 - The FACETS project ended. This started in 2005 and was the precursor to BrainScaleS.
01.Jan.2011 - BrainScaleS project start.
25.Aug.2011 - Neural net wafers delivered from the UMC fab.
14.Sep.2011 - First spikes seen from the wafer.
27.Jan.2012 - First communication between on-wafer neurons.


Heidelberg University is leading the research project. The neuromorphic hardware is being developed in Heidelberg and Dresden. The other universities involved are as follows:

People involved

Project coordinator: Karlheinz Meier  Homepage

Alexander Kononov   Homepage
  Andreas Grübl   Linkedin profile Facebook profile Homepage
Post-doctoral researcher 
  Bernhard Kaplan   Google profile Facebook profile Homepage
KTH Stockholm 
Bernhard Vogginger   Twitter profile
  Björn Kindler   Homepage
Heidelberg, project admin 
  Dan Husmann   Homepage
Daniel Brüderle   Homepage
Heidelberg, postdoc researcher 
  Eric Müller   Google profile Homepage
  Holger Zoglauer  
Johannes Schemmel   Linkedin profile Twitter profile Homepage
  Karlheinz Meier   Homepage
Heidelberg, project coordinator 
  Marc-Olivier Schwarz   Google profile Linkedin profile Twitter profile Facebook profile Homepage
PhD candidate 
Mihai Petrovici   Homepage
  Ranjeet Kuruvilla  
  Sebastian Jeltsch   Homepage
Thomas Pfeil   Google profile Homepage
  Venelin Petkov   Google profile