DARPA SyNAPSE Program
SyNAPSE is a DARPA-funded program to develop electronic neuromorphic machine technology that scales to biological levels. More simply stated, it is an attempt to build a new kind of computer with similar form and function to the mammalian brain. Such artificial brains would be used in robots whose intelligence matches that of mice, cats, and ultimately humans.
SyNAPSE is a backronym standing for Systems of Neuromorphic Adaptive Plastic Scalable Electronics. It started in 2008 and as of November 2011 has received $78.6 million in funding. It is scheduled to run until around 2016. The project is contracted to IBM, Hewlett-Packard, HRL Laboratories, and five leading US universities.
The ultimate aim is to build an electronic microprocessor system that matches the human brain in function, size, and power consumption. It should recreate 10 billion neurons, 100 trillion synapses, consume 1 kilowatt (the same power as a small electric heater), and occupy 2 liters of space.
In November 2009 it was announced that a cat-scale neocortex had been successfully simulated at ~643x slower than real time using a Blue Gene P supercomputer at the Lawrence Livermore National Laboratory. In October 2011 a neuromorphic chip was unveiled containing 256 neurons and ~100,000 synapses that could recognise digits and play a game of pong. Work continues on larger simulations and the building of chips containing more neurons.
Background
The following text is taken from the Broad Agency Announcement put out by DARPA in April 2008 (see original):
Over six decades, modern electronics has evolved through a series of major developments (e.g., transistors, integrated circuits, memories, microprocessors) leading to the programmable electronic machines that are ubiquitous today. Owing both to limitations in hardware and architecture, these machines are of limited utility in complex, real-world environments, which demand an intelligence that has not yet been captured in an algorithmic-computational paradigm. The SyNAPSE program seeks to break the programmable machine paradigm and define a new path forward for creating useful, intelligent machines.
The vision for the DARPA SyNAPSE program is the enabling of electronic neuromorphic machine technology that is scalable to biological levels. Programmable machines are limited not only by their computational capacity, but also by an architecture requiring human-derived algorithms to both describe and process information from their environment. In contrast, biological neural systems autonomously process information in complex environments by automatically learning relevant and probabilistically stable features and associations. Since real world systems are always many body problems with infinite combinatorial complexity, neuromorphic electronic machines would be preferable in a host of applications - but useful and practical implementations do not yet exist.
The key to achieving the vision of the SyNAPSE program will be an unprecedented multidisciplinary approach that can coordinate aggressive technology development activities in the following areas: 1) hardware; 2) architecture; 3) simulation; and 4) environment.
- Hardware implementation will likely include CMOS devices, novel synaptic components, and combinations of hard-wired and programmable/virtual connectivity. These will support critical information processing techniques observed in biological systems, such as spike encoding and spike time dependent plasticity.
- Architectures will support critical structures and functions observed in biological systems such as connectivity, hierarchical organization, core component circuitry, competitive self-organization, and modulatory/reinforcement systems. As in biological systems, processing will necessarily be maximally distributed, nonlinear, and inherently noise- and defect-tolerant.
- Large scale digital simulations of circuits and systems will be used to prove component and whole system functionality and to inform overall system development in advance of neuromorphic hardware implementation.
- Environments will be evolving, virtual platforms for the training, evaluation and benchmarking of intelligent machines in various aspects of perception, cognition, and response.
Realizing this ambitious goal will require the collaboration of numerous technical disciplines such as computational neuroscience, artificial neural networks, large-scale computation, neuromorphic VLSI, information science, cognitive science, materials science, unconventional nanometer-scale electronics, and CMOS design and fabrication.
Current status
Current status: A third tranche of funding, worth $21m, was received August 2011 for phase 2. Originally one of the main aims of this phase was to demonstrate a simulated neural system of ~106 neurons performing at mouse level in the virtual environment.
Project phases
No phase should be more than 18 months. The following targets were specified in 2008 before the project started. The targets for each phase may have changed in the meantime depending on the outcome of completed phases.
Phase 0
Feasibility study for nine months. Funding of ~$4.9m. Started November 2008, completed ~August 2009.
Hardware: Demonstrate an electronic synaptic component exhibiting spike-timing-dependent plasticity (STDP) with:
- Synaptic density scalable to >1010/cm2
- Operating speed >10 Hz
- Consumes < 10-12 Joules per synaptic operation at scale
- Dynamic range of synaptic conductance > 10
- Synaptic conductance increase >1%/pulse for presynaptic spike applied somewhere <80-1 msec before a postsynaptic spike
- Synaptic conductance decrease >1%/pulse for presynaptic spike applied somewhere within 1-80 msec after postsynaptic spike
- 0%-0.02% conductance decrease if presynaptic spike applied > 100 msec before or after postsynaptic spike
- Performance maintained over 3 x 108 synaptic operations
Architecture: Specify and validate by simulation the function of core microcircuit assemblies using measured synaptic properties. The chosen microcircuits must support the larger system architecture and demonstrate spike time encoding, spike time dependent plasticity, and competitive neural dynamics.
Phase 1
In August 2009 IBM received $16.1 million in funding to carry out phase 1. The phase started ~November 2009 and completed ~July 2011.
- Demonstrate all core micro-circuit functions in hardware
- Specify a chip fabrication process supporting the architecture with > 1010 synapse/cm2, > 106 neurons/cm2
- Demonstrate a neuromorphic design methodology that can specify all the components, subsystems, and connectivity of a complete system
- Specify a corresponding electronic implementation of the neuromorphic design methodology supporting > 1014 synapses, > 1010 neurons, mammalian connectivity, < 1 kW, < 2 L
- Simulation: Demonstrate dynamic neural activity, network stability, synaptic plasticity, and self-organization in response to sensory stimulation and system-level modulation/reinforcement in a system of ~106 neurons
- Environment: Demonstrate virtual Visual Perception, Decision and Planning, and Navigation Environments with a selectable range of complexity corresponding roughly to the capabilities demonstrated across a ~104 range in brain size in small-to-medium mammalian species
Phase 2
As of November 2011 this is the current phase. Funding of $21m received by IBM in August 2011.
- Chip fabrication of >1010 synapse/cm2, >106 neurons/cm2
- Design a complete neural system of ~1010 synapses and ~106 neurons for simulation testing
- Design a corresponding single chip neural system of ~1010 synapses and ~106 neurons
- Demonstrate a simulated neural system of ~106 neurons performing at mouse level in the virtual environment
- Expand the Sensory Environment to include training and evaluation of Auditory Perception and Proprioception
- Expand the Navigation Environment to include features stressing Competition for Resources and Survival
- Demonstrate a selectable range of complexity corresponding roughly to the capabilities demonstrated across a ~106 range in brain size mammalian species
Phase 3
Estimated to begin between late 2012 and late 2013.
- Fabricate a single-chip neural system of ~106 neurons (1 million) into a fully functioning assembly. Show mouse-level performance in virtual environment.
- Design neural system of ~1012 synapses (1 trillion) and ~108 neurons (100 million) for simulation testing
- Design a corresponding single-chip neural system of ~1012 synapses (1 trillion) and ~108 neurons (100 million)
- Demonstrate a simulated neural system of ~108 neurons performing at cat level
- Add touch to the sensory environment.
- Add a symbolic environment.
Phase 4
The final deliverable metric is the fabrication of a multi-chip neural system of 108 neurons (100 million) and install this in a robot that performs at cat level. Estimated to begin between late 2013 and late 2015. Estimated completion date, late 2014 to late 2017.
Technical details
Cat-scale simulation
IBM developed a massively parallel cortical simulator called C2. It ran on the Blue Gene/P supercomputer named Dawn at Lawrence Livermore National Laboratory. The supercomputer had 147,456 CPUs and 144 TB of main memory. The largest cortical simulation consisted of 1.6 billion neurons and 8.87 trillion synapses. This matches the scale of a cat cortex and 4.5% the scale of a human cortex. The simulation ran at 643 times slower than real time. The simulations incorporated single-compartment spiking neurons, STDP, and axonal delays. The simulation time step was 0.1 milliseconds.
The architecture and connectivity of the simulated network was biologically inspired (see image right).
It included the visual cortex,
attendant sections of the thalamus,
and the reticular nucleus.
Regions of the simulated cortex were constructed from thalamocortical modules.
Each module had 10,000 cortical neurons, 334 thalamic neurons,
and 130 reticular nucleus neurons. Within each module, cortical neurons were further sub-divided into four layers
(real mammalian brains have six layers).
The ratio of exitatory to inhibitory neurons was also modelled on experimentally observed data.
The largest model had 278 x 278 modules making a total of 1.6 billion neurons.
The BrainCam was a framework that recorded the firing of all neurons and converted them to a movie for convenient visualisation - similar in concept to an EEG trace. A video (150 MB mpeg) is available showing how a stimulus in the shape of the letters "IBM" propagates. The speed and pattern of propagation matches observations made in animals. The SpikeStream was framework to supply sensory stimulus information encoded in spikes. The spikes were encoded to represent geometric visual objects and auditory utterances of the alphabet.
Future plans are to enrich the model with long-distance connectivity between cortical areas. Also, to increase resolution by reducing the size of each module from 10k neurons down to 100 neurons - to pair with latest experimental results. It is predicted that a 100% human scale, real-time simulation would require 4 petabytes of memory and a supercomputer running at >1 exaflops. This should be achieved by the year 2018 if advances continue at the same rate as recent decades.
Published paper: The Cat is Out of the Bag: Cortical Simulations with 109 Neurons, 1013 Synapses (PDF) - November 2009
Neuromorphic processor
In August 2011 IBM revealed that they had built a digital neurosynaptic core. The microprocessor implements 256 leaky integrate-and-fire neurons in CMOS hardware. The neurons are arranged in a 16x16 array. Each neuron is connected to others by 1,024 synapses, making a total of 262,144 synapses per core.
A 45 μm SOI manufacturing process was used. 45 μm was state of the art in retail laptop computers in 8 (modern laptops are now 32 nm, with 22 nm just announced in November 2011). The entire core has 3.8 million transistors and fits inside 4.2 mm2. Each neuron occupies 35 μm x 95 μm (compare this to a real neuron body which is about 10 μm2).
The core was mounted on a custom-built printed circuit board built and connected to a personal computer via USB. This way it could be interfaced to various virtual and real environments. The core learned to recognise hand-written digits (see video) and could also play a game of pong (see video).
The core was completely deterministic. This is unlike previous analog neuromorphic hardware which is sensitive to construction variations and ambient temperatures. The chip had a ~1 kHz clock, corresponding to ~1 ms biological time step. Internally also ~1 mHz clock for other stuff (what exactly?).
Unlike the traditional Von Neumann computer architecture, the computation and memory units of this chip are tightly integrated. This speeds up highly parallel computation as well as reducing the power required. It is theoretically possible to build a large on-chip network of these cores, thus creating an ultra-low power "neural fabric" for a wide array of real-time applications. The ultimate aim is to build a human-scale system with 1014 synapses.
Papers
- A Digital Neurosynaptic Core using Embedded Crossbar Memory with 45pJ per spike in 45nm
- A 45nm CMOS Neuromorphic Chip with a Scalable Architecture for Learning in Networks of Spiking Neurons
Funding
All funding for the SyNAPSE program comes from DARPA. Total funding per fiscal year is as follows. Note that US government fiscal years begin on October 1. So FY 2009 ran from October 1, 2008 to September 30, 2009.
- FY 2008 - $0 (project started October 2008)
- FY 2009 - $3,000,000 (PDF, page 24)
- FY 2010 - $17,025,000 (PDF, page 19)
- FY 2011 - $27,608,000 (PDF, page 15)
- FY 2012 - $31,000,000 (PDF, page 4)
- Total: $78,633,000
The above funds were split between the various collaborators. The exact split is not public knowledge.
On November 20, 2008 it was announced that IBM and its collaborators had been selected and were awarded $4,879,333. This was to fund phase 0, the nine-month feasibility study. Announcement and IBM press release.
In August 2009 a further $16.1 million was awarded to carry out phase 1. IBM press release from November 18, 2009.
In August 2011 an additional ~$21 million was awarded to IBM for phase 2. IBM press release from August 18, 2011. Further funding for phase 2 was also awarded to HRL labs, see their press release. The amount received by HRL is unknown.
Timeline
| 2007 | April - Todd Hylton joins DARPA | |
| 2008 |
April 9 - DARPA put out a solicitation for applications (announcement).
May 22 - Due date for initial proposals. October - Winning contractors announced | |
| 2009 | November - announcement of successful cat-scale simulation | |
| 2010 | ||
| 2011 | August - announcement of successful neuromorphic chip implementation | |
| 2012 | ||
| 2013 | ||
| 2014 | ||
| 2015 | ||
| 2016 | Program end |
Criticism
Other non-participating research groups have raised criticisms about this project. Details to follow.
Dr. Markram of the Blue Brain Project describes how
IBM's cat-brain claims are a hoax.
Massimiliano Versace's critique of the IBM cognizer chip announced August 2011:
neurdon.com / ibm-cognizer
Participating organisations
The following organisations are participating in the DARPA SyNAPSE program: (ref, ref)
- DARPA
- lead by Todd Hylton
- IBM Research - lead by Dharmendra Modha
- Hewlett-Packard Laboratories - lead by Greg Snider
- HRL Laboratories
- lead by Narayan Srinivasa
(press release)
- Columbia University Medical Center - lead by Stefano Fusi
- Cornell University - lead by Rajit Manohar
- Stanford University - lead by Brian Wandell and Philip Wong
- University of California, Merced - lead by Christopher Kello
- University of Wisconsin-Madison - lead by Giulio Tononi
Other collaborators:
- Neuromorphics Lab at Boston University
led by Massimiliano Versace.
Supported via internal HP funding, i.e. independent of government support.
The project is called MoNETA - an artificial whole brain system.
People involved
Andrew Cassidy   Circuits, IBM Research - Almaden | Arnon Amir   Simulation, IBM Research - Almad | Ashutosh Saxena  Environment, Cornell University | ||
| Benjamin Parker Circuits, IBM Research - Watson | Bernard Brezzo Circuits, IBM Research - Watson | Brian Wandell  Stanford University | ||
| Charles Alpert Circuits, IBM Research - Austin | Christopher Kello Environment, University of Calif | Dan Friedman Circuits, IBM Research - Watson | ||
| Daniel Ben-Dayan Rubin Simulation, IBM Research - Almad | David Woodruff Simulation, IBM Research - Almad | Davis Barch Simulation, IBM Resesarch - Alma | ||
| Dharmendra Modha IBM Almaden Research Center in S | Fadi Gebara Circuits, IBM Research - Austin | Giulio Tononi Simulation, University of Wiscon | ||
| Greg Snider HP principal investigator | Ivan Vo Circuits, IBM Research - Austin | Jae-Sun Seo Circuits, IBM Research - Watson | ||
| John V. Arthur Circuits, IBM Research - Almaden | Jose Tierno Circuits, IBM Research - Almaden | Jun Sawada Circuits, IBM Research - Austin | ||
| Kavita Prasad Circuits, IBM Research - Almaden | Ken Clarkson Simulation, IBM Research - Almad | Leland Chang Circuits, IBM Research - Watson | ||
| Mark Ferriss Circuits, IBM Research - Watson | Massimiliano Versace Leads the Neuromorphics Lab at B | Michael Beakes Circuits, IBM Research - Watson | ||
| Mohit Kapur Circuits, IBM Research - Watson | Narayan Srinivasa HRL principle researcher, team l | Pallab Datta Simulation, IBM Research - Almad | ||
| Paul Merolla Circuits, IBM Research - Almaden | Paul Maglio Environment, IBM Research - Alma | Philip Wong Stanford University | ||
| Raghavendra Singh Simulation, IBM Research - India | Rajit Manohar Circuits, Cornell University | Robert Montoye Circuits, IBM Research - Watson | ||
| Rodrigo Alvarez-Icaza Circuits, IBM Research - Almaden | Sameh Asaad Circuits, IBM Research - Watson | Scott Hall Circuits, IBM Research - Almaden | ||
| Seongwon Kim Circuits, IBM Research - Watson | Shyamal Chandra Environment, IBM Research - Alma | Stefano Carpin Environment, University of Calif | ||
| Stefano Fusi Simulation, Columbia University | Steven Esser Simulation, IBM Research - Almad | Ted Wong Simulation, IBM Research - Almad | ||
| Todd Hylton DARPA, program creator and manag | Tom Zimmerman Environment, IBM Research - Alma | Tuyet Nguyen Circuits, IBM Research - Austin | ||
| Vitaly Feldman Simulation, IBM Research - Almad | Yong Liu Circuits, IBM Research - Watson |
The IBM SyNAPSE team pictured in November 2008.
Click for the original copy.
Science papers
-
A Digital Neurosynaptic Core using Embedded Crossbar Memory with 45pJ per spike in 45nm
September 2011, Paul Merolla, John Arthur, Filipp Akopyan, Nabil Imam, Rajit Manohar, Dharmendra S. Modha -
A 45nm CMOS Neuromorphic Chip with a Scalable Architecture
for Learning in Networks of Spiking Neurons
September 2011, Jae-sun Seo, Bernard Brezzo, Yong Liu, Benjamin D. Parker, Steven K. Esser, Robert K. Montoye, Bipin Rajendran, Jose A. Tierno, Leland Chang, Dharmendra S. Modha, and Daniel J. Friedman -
The Cat is Out of the Bag: Cortical Simulations with 109 Neurons, 1013 Synapses
November 2009
Videos
- IBM lab tour by Dean Takahashi of Venture Beat, 2011
- Dharmendra Modha interview with Robert Scoble
- IBM SyNAPSE, overview
- IBM SyNAPSE, brain vs. computer
- IBM SyNAPSE, hardware
- IBM SyNAPSE, circuit architecture
- IBM SyNAPSE, software
Weblinks
- darpa.mil / synapse - DARPA project homepage
- ibm.com/synapse - IBM homepage for the project
- wikipedia.org/wiki/SyNAPSE - Wikipedia article
- venturebeat.com / ibm-brain-chips - article, video, and tour of the IBM lab
- neurdon.com / ibm-cognizer - a critique of the IBM cognizer chip announced August 2011
