SpiNNaker brain simulation machine

SpiNNaker is a massively-parallel neuromorphic computing architecture designed to model very large, biologically-plausible spiking neural networks in real-time. A SpiNNaker machine will consist of 65,536 homogeneous eighteen-core processors, each with an on-board router which forms links with neighbouring chips.

The machine is built to mimic a brain's biological structure and functionality. It will exhibit massive parallelism and redundancy, as well as resilience to an unreliable environment and failure of individual components. With a million cores, and 1,000 simulated neurons per core, the machine will be capable of simulating a billion neurons. This equates to approximately the scale of the cat brain brain (300 million cortical neurons) or 1% of the human brain (~100 billion neurons).

Rather than implement a particular algorithm, SpiNNaker will be a resource. Different types of neural networks can be designed and run on the machine, simulating different kinds of neurons and connectivity patterns. SpiNNaker is a contrived acronym derived from Spiking Neural Network Architecture.

The British project is lead by Professor Steve Furber at Manchester University and involves collaborators from the universities of Southampton, Cambridge, and Sheffield. The project started in 2005 and is currently funded until early 2014. The microchips were delivered in June 2011. Small networks have been tested. The full billion-neuron machine is due to be finished by the end of 2012.

Contents

Hardware description

The SpiNNaker machine is comprised of up to 65,536 custom-built microchips. Each chip is connected to six neighbours, forming a toroidal network.

One chip contains 18 identical fasicles clocked at 200 MHz. A fasicle contains an ARM968 processor core, 32 kB of instruction memory, 64 kB of data memory, three controllers, a clock, and a timer.

Each multiprocessor chip has about 100 million transistors, most of which are in the 55 blocks of 32 kB SRAM local instruction and data memory. They were manufactured using an 130 nm process. Although the ARM968 is relatively old, it is used because the licensing agreement was committed to back in 2005.

On a separate die, but within the same chip package, is a 128 MB DDR SDRAM memory chip that operates at up to 166 MHz. This has about a billion transistors. The multiprocessor and memory chips are packaged together, one above the other, in a 19x19mm 300-pin ball grid array.

Each core dissipates 1 Watt of energy. The SpiNNaker machine is expected to consume 50-100 kW peak, although the average is predicted to be well below 50 kW. For comparison, the average human brain consumes around 20 W.

The finished million-processor machine will occupy several cabinets. At least six to eight, possibly more if the power density turns out to be an issue.

A possible configuration would be: ~30 chips per board, ~30 boards per rack, ~12 racks per cabinet, 6 cabinets. This is a purely speculative configuration dreamt up by this article's author.

Modelling capabilities

The SpiNNaker machine has a million processor cores. Each core can model a variable number of neurons, but a typical number will be a thousand. This makes for a total of a billion simulated neurons. The SpiNNaker brain machine is thus approximately on the same scale as a honey bee brain which has 960,000 neurons, or about 1% the size of the human brain, which has 100 billion neurons. See a full list of animals by number of neurons.

Each processor core is programmable. It can implement any model that fits in its 32 kB instruction memory. In this sense the SpiNNaker machine can be considered an FPGA for neurons.

Signalling within the SpiNNaker chip is enterely digital, not analog. Each spike is a 40-bit packet containing a 32-bit identifier of the source neuron.

Each chip connected, asynchronously to six neighbours. The topology of the simulated neural network, however, is completely independent of the physical hardware design. In a typical simulation a neuron would have around 1,000 synapses.

It is anticipated that the machine will be useful for modelling and understanding the processes of learning, memory, and STDP in spiking neural networks.

Chip manufacture

The SpiNNaker machine and it's multiprocessor chips were designed in Manchester, UK.

The multiprocessor die were manufactured by United Microelectronics Corporation (UMC) in Taiwan.

The accompanying memory die is an off-the-shelf 128 MB DDR SDRAM from Micron Technology in Idaho, US.

The multiprocessor and memory were mounted together, one above the other, in a 300-BGA package. The packaging was done by Unisem Europe near Crumlin, Wales.

Current status

Chips delivered June 2011
Small simulations running now (as of second half of 2011)
Scaling up to billion neuron simulation by end 2012
  (eetimes.com/electronics-news/4217840/Million-ARM-cores-brain-simulator)

Current system has 8 processors, system with 16 coming soon 
At the moment [July 2011], the researchers are testing the system with a card
  containing four ARM processors, giving 72 cores in total;
they then hope to expand this and build a card-based system of 1,000 cores
  [that'll be the 8x8 chips = 8x8x18=1000 cores].
By the end of the year [2011] the researchers hope to assemble a SpiNNaker
  architecture with 10,000 cores [555 chips]

Prospects

http://www.theregister.co.uk/2011/07/07/arm_project_spinnaker_super/page2.html
If Moore's New Law - the number of cores on a chip doubles every 18 months
can hold for the next 25 years, then we'll be at a million cores or so per chip.
So a hundred of those cores - call it a rack - should be able to simulate a human brain.

It can currently only simulate 1% of the brain, size of a honey bee brain
but if it proves successful this can be scaled up as advances in microchips progress

Timeline

ARM was approached in May 2005
Architectural commitments in 2006
Prototype chips were first made in 2009 and a four chip test board has been evaluated
Next step is to plan a board with 8x8 chips on it - 1,153 cores - 1,152,000 neurons 
Full SpiNNaker machine expected to be complete by end of 2012

Funding

Current funding is a £4,906,665 UK government grant from the EPSRC. That is split between four universities as follows:

  • Professor S B Furber, Manchester, UKP 2,707,120, 01.Jan.2009 - 31.Dec.2013 G015740
  • Professor AD Brown, southampton, UKP 892,622, 01.Mar.2010 - 28.Feb.2014 G015775
  • Dr SW Moore, Cambridge, UKP 723,230, 01.Apr.2009 - 31.Mar.2014 G015783
  • Professor DJ Allerton, Sheffield, UKP 583,693, 15.Jun.2009 - 14.Jun.2014 D07908X

Previous funding:

  • D07908X £637,840 to manchester, 1.oct.2006 - 31.Mar.2010
  • D079594 £393,925 to southhampton, 1.oct.2006 - 31.Mar.2010

People involved

Universities of Manchester, Southampton, Cambridge, and Sheffield

Lead by Professor Steve Furber (G, L, W, H) from Manchester. He designed the BBC Micro processor system, and the original ARM microprocessor.

Andrew Brown leads at the University of Southampton

List of other staff.

Research papers